This invention relates to a mask read only memory (ROM), and more particularly to a structure and method for manufacturing a read only memory with a spacer film.
A mask programmable ROM is occasionally called a mask ROM. In data processing systems, a mask ROM is used for memorizing game contents in a game chip, or for storing control logic such as a microprogram. It is desirable that the control logic be integrated with high density and occupy smaller area. There is disclosed a ROM structure having a series-connected NAND logic as a ROM structure used for memorizing relatively by far more information of control logic in a fixed area. The art is disclosed in U.S. Pat. No. 4,142,176. The prior art is a ROM structure in which a plurality of depletion-mode and enhancement-mode transistors are arranged in the form of a series-connected NAND logic matrix. Gates of the transistors on each row share one row line, with sources and drains of adjacent transistors placed in a string of each column are connected in series in an electrical manner on each column.
Therefore, in such a ROM structure of NAND logic type, an insulating layer on the sources and drains of adjacent transistors in a string has been used as an insulator for separating row lines therebetween. However, in a ROM which includes a plurality of series-connected transistors arranged in an array of rows and columns, a ROM structure having the sources and drains, and an insulating layer thereon can not provide a higher integrated-density in a fixed area.